At-Speed Test Methods for LSSD and Mux Flip-Flop Designs – Best Practices

At-speed scan testing has become necessary to detect the growing population of timing defects in today’s nanometer-scale process. There are several at-speed delay test methods available in the industry to generate the delay patterns. Manufactures are continuing to look for ways to improve the effectiveness of at-speed delay test. The key is to create high quality, cost effective tests for these complex nanometer designs. This paper describes an efficient at-speed test implementation technique known as improved launch delay test with level sensitive scan design (LSSD) and mux scan flip-flop design which in turn achieve high quality cost effective delay test patterns. The importance of small delay defect testing and sources of chip overkill are also brought together in this paper as they are inevitable factors with at-speed test techniques. At the end of the paper the best suitable flow and recommendations for the optimized patterns with good coverage during at-speed testing are explained.